1. Field of the Disclosure
The present disclosure generally relates to processing systems and, more particularly, to memory systems for processing systems.
2. Description of the Related Art
The memory found in processing systems often includes features such as error correcting codes (ECC) to improve data storage reliability. These reliability features provide for the detection and correction of transient errors when data is retrieved from the memory. Some memories may also include features to address more permanent errors resulting from manufacturing defects. For example, some memory devices include a conventional row redundancy mechanism whereby spare rows of memory cells are incorporated directly into the array. The spare cells and associated logic are used to logically “replace” a defective row (i.e., a row of memory cells having one or more defective memory cells). Typically, spare rows are enabled by selectively blowing fuses within a spare row decoder to match the address of the rows having defective memory cells. These fuses are often programmed during manufacture at testing stage of the wafer, die or completed and packaged memory device.
The use of the same reference symbols in different drawings indicates similar or identical items.